This application relies for priority upon Korean Patent Application No. 2001-34183, filed on Jun. 16, 2001, the contents of which are herein incorporated by reference in their entirety.
The present invention generally relates to universal serial bus systems, and more specifically to a data transmission circuit having low-speed output drivers to control crossover voltages in universal serial bus systems.
In accordance with the latest developments of functions in computer processors and application programs, it has become necessary to efficiently expand the connection capacity of computers for various kinds of peripheral devices. Conventional external ports of computer systems have already come up to limits of certain peripheral devices with various functions and interface forms. For those demands, a new bus interface system, referred to as the xe2x80x9cuniversal serial busxe2x80x9d (hereinafter, referred to as xe2x80x9cUSBxe2x80x9d), has been developed by major computer and telephone networks companies, such as Intel, Microsoft, Compaq, NEC, and so on, in order to provide practical applications adaptable to various interfacing needs. The USB now has become a new standard for interfacing between computers and peripheral devices. The USB standard V1.0 was first defined on Jan. 15, 1996, and was revised as USB V1.1 on Jul. 28, 1998.
The USB device can be assigned to a multiplicity of peripheral devices in number of, for example, 127. One peripheral device includes 16 end points. Accordingly, it is possible to grant 16 functions at maximum in one peripheral device. There can be various peripheral devices connectable to USB devices, such as telephones, MODEMs, printers, scanners, game pads, microphones, digital speakers, styluses, joysticks, mice, monitors, or digital cameras.
Interface cables connecting a host computer to a peripheral device, or connecting between peripheral devices, are composed of a power source voltage (VDD) line, a ground voltage line (VSS), and a pair of data signal lines (D+, Dxe2x88x92). The data signals must be leveled in the CMOS voltage range of 3.3V, as an example.
The USB V1.1 also defines optional speed modes of high-speed and low-speed. The high-speed mode is operable at 12 Mbps (mega bits per second) while the low-speed mode is operable at 1.4 Mbps. In the low-speed mode, since bus occupation rate becomes eight times that of the high-speed mode, it badly affects data transmission conditions for high frequency devices when too many devices are connected or short cycles are dominant in processing data. Therefore, the low-speed mode is adaptable to devices in need of low cost and low power consumption, or to devices with smaller amounts of data transmission, such as a mouse or a keyboard.
The pair of data signals (D+, Dxe2x88x92) is a complementary pair in which one is at a high level when the other is at a low level. The data signal is designed to rise up to a high level or to fall down to a low level, with a predetermined slope. According to the USB standard, a crossover voltage, i.e., a voltage point where one data signal slope rising to a high level from a low level meets the other data signal slope falling to a low level from a high level, should be within the range of between 1.3V and 2.0V. FIG. 1A shows an ideal case where a crossover voltage of the data signals complies with the range defined in the USB standard while, FIG. 1B illustrates an abnormal case where a crossover voltage of the digital signals does not comply with the USB standard range.
Transmission data in the form of NRZI (Non-Return-to-Zero-Invert) are converted into bus-specific data signals (D+, Dxe2x88x92), which are modulated by a transceiver to be adaptable to USB cables. A crossover voltage of the bus-specific data signals is sensitive to the threshold voltages of transistors used in the transceiver. For instance, assuming that a distribution profile of threshold voltages is 0.9Vxc2x10.1V, the threshold voltages ranges from 0.8V at minimum to 1.0V at maximum. As a result, there occur differences between a rising time and a falling time, which causes variation of crossover voltage of the bus-specific data signals.
It is, therefore, an object of the present invention to provide a data transmission circuit having a USB low-speed transceiver capable of regulating a crossover voltage of bus-specific data signals to be in a normal range by offsetting variations arising from manufacturing processes.
The data transmission circuit has a test mode for offsetting variation of crossover voltages of the first and second data signals, which rises from threshold voltage distribution of plural transistors embedded in a transceiver. The transceiver converts an external test clock signal into the first and second data signals to be transferred to the first and second data lines, making the first and second data signals be set with predetermined delay times. The delay times of the first and second data signals are adjusted when those crossover voltages deviate from a predetermined range, so that the crossover voltages of bus-specific data signals generated from the USB low-speed transceiver are always positioned within a normal range.
According to an aspect of the present invention, there is provided a data transmission circuit for transferring first and second data signals onto first and second data lines, respectively. The circuit includes a selection circuit for outputting an external data input signal in a normal mode while outputting an external test clock signal, an output circuit for converting an output signal from the selection circuit into the first and second data signals with predetermined delay times, and a comparison circuit for checking whether or not a crossover voltage of the data signals is positioned within a predetermined range. The data signals are adjusted with delay times when the crossover voltage deviates from the predetermined range.
In one embodiment, the comparison circuit includes a first circuit, e.g., comparator, for checking a first time point at which the first data signal reaches a reference voltage; a second circuit, e.g., comparator, for checking a second time point at which the second data signal reaches the reference voltage; and a third, e.g., logic, circuit for checking whether the first and second time points match with each other, such as, for example, by using an exclusive OR operation.
The data transmission circuit can also include a counter for counting a maintenance time of an active period of an output signal generated from the logic circuit. The delay times of the data signals can increase in accordance with counting values provided from the counter.
In one embodiment, the data transmission circuit is employed in an electronic device adaptable to USB standard V1.1, and the data lines are applicable to a USB interface. The reference voltage is from 1.3V to 2.0V.
In another aspect of the invention, a data transmission circuit transferring first and second data signals onto first and second data lines, respectively, includes a first selection circuit for outputting an external data input signal in a normal mode while outputting an external test clock signal; a second selection circuit for outputting a complementary signal of the external data input signal in a normal mode while outputting a complementary signal of the external test clock signal; a first delay circuit for delaying an output signal of the first selection circuit by a predetermined time; a second delay circuit for delaying an output signal of the second selection circuit by a predetermined time; a first output circuit for converting an output signal of the first delay circuit to the first data signal to be transferred into the first data line; a second output circuit for converting an output signal of the second delay circuit to the second data signals to be transferred into the second data line; and a comparison circuit for checking whether a crossover voltage of the data signals is positioned within a predetermined range during the test mode. The data signals are adjusted with delay times when the crossover voltage deviates from the predetermined range.
In still another aspect of the invention, a data transmission circuit is included in a serial interface device used in conducting interface operations between a serial data bus of a digital data processing system and function devices offering additional functions to the system. The serial interface device includes a controller for converting a data signal from the function device into an interface-specific data signal and for generating plural control signals. A data transmission circuit transfers first and second data signals onto first and second data lines, respectively. The circuit includes a selection circuit for outputting an external data input signal in a normal mode while outputting an external test clock signal; an output circuit for converting an output signal from the selection circuit into the first and second data signals with predetermined delay times; and a comparison circuit for checking whether a crossover voltage of the data signals is positioned within a predetermined range. The data signals are adjusted with delay times when the crossover voltage deviates from the predetermined range.